The present invention relates generally to electrically programmable non-volatile memory cells and arrays, and, more particularly, to electrically erasable programmable non-volatile memory cells and arrays where memory cells in a memory array can be selectively altered on a byte-block basis.
There are several types of memory cell structures in the field of non-volatile memory.
One type of non-volatile memory uses a storage transistor having a so-called floating gate. The floating gate is generally fabricated between the control gate and the substrate and is not directly connected to any terminals or any specific structures. If the floating gate is neutral (no or minimal charges stored), it does not affect the electric field generated by the control gate that affects the channel region between the source and drain terminals. In effect, the storage transistor operates like a normal MOS transistor. If the floating gate is charged (storing electrons), the electrons in the floating gate react to the electric field generated by the control gate and generate an electric field in the channel region that is opposite in polarity to the electric field generated by the control gate. From this technology, a class of non-volatile memory devices known as electrically erasable programmable read only memory or EEPROM has been developed.
Referring to FIG. 1a, one type of EEPROM storage transistor cell structure is the FLOTOX (Floating Gate Tunnel Oxide) cell structure. Here, there is a polysilicon control gate 10 where a control voltage VCG may be applied, a polysilicon floating gate 12, a source terminal having a source voltage potential VS, a drain terminal having a drain voltage potential VD, and another polysilicon 14 over two n-type regions, 16 and 18, forming a select transistor. An inter-poly dielectric region 26 is defined between the two polysilicon pieces 10 and 12 (control gate and floating gate); two gate-dielectric regions 28 and 32 are defined by the respective polysilicon areas; and a tunnel dielectric region is defined by the tunnel window region 22 of the polysilicon piece 12 (floating gate). Due to the unique shape of the control gate 10 and the floating gate 12, a tunnel window region 22 is defined to allow the tunneling of electrons. This cell structure may be schematically represented as in FIG. 1b where a FLOTOX transistor 36 is coupled with a select transistor 38. In operation, the select transistor 38 has to be turned on in order to operate the FLOTOX transistor 36.
Programming of the FLOTOX memory cell is carried out by applying a relatively high voltage pulse between the control gate 10 and the drain terminal 18 when there is a positive voltage applied at the select gate terminal 14. The high voltage pulse initiates carrier generation in the substrate and causes electrons to penetrate the tunnel-dielectric region 30 and accumulate in the floating gate 12. In a likewise manner, in erasing the memory cell, an inverse voltage is applied between the gate and drain terminals. Thus, the negative electrons in the floating gate are drawn to the drain through the thin tunnel oxide.
The erase and program operations are achieved by taking advantage of the Fowler-Nordheim tunneling mechanism occurring between the floating gate 12 and the silicon substrate 24 through a thin oxide called the tunnel oxide 30. A tunnel window 22 defines the area of the tunnel oxide where a large tunnel window would improve the speed of the erase/program operation but would also increase the cell size as well. A thinner tunnel oxide region 30 would reduce the tunneling voltage requirement and reduce the erase/program operation time. However, such a memory cell is more difficult to manufacture and may have greater reliability problems.
There are several problems with the FLOTOX memory cell. The memory cell requires a conductive n-type region on the p-type substrate 24 directly in the tunnel window area 22. Since this n-type region can not be fabricated by the self-alignment method, it requires an additional processing step which translates to higher processing cost and lower yield. Additionally, an electric field of about 10 mega volt per centimeter is required for tunneling to occur through the oxide, which translates to a voltage potential difference between the control gate and the drain terminal in the range from 16 volts to 20 volts. This is a relatively high voltage requiring special drain and source formation (at the drain 18 and source 34 terminals for the select transistor and at the drain terminal 34 for the FLOTOX transistor). These high voltage junctions would in turn require the select transistor to have a longer channel or have an overall larger area. The traditional FLOTOX erase and program operation time are typically in the range of 1 ms to 3 ms each with approximately 18 to 20 volts applied. The total write time for this type of memory cell is 10 ms maximum.
Referring to FIG. 2a, another important type of non-volatile memory is the flash memory. In a flash memory cell, there is a drain (40 or 42) and source (40 or 42) region deposited on and within a substrate 44. An insulating layer is deposited over the substrate and the drain and source regions, 50 and 52. Over the insulating layer, a floating gate 48 is disposed in such a manner to partially overlap one of the regions. A second insulating layer is then deposited over the floating gate 48. A control gate 46 is then disposed over the floating gate 48 and partially overlapping the other region.
In operation, the flash memory cell is erased when the drain and source terminals are connected to ground and a high voltage is applied at the control gate 46, causing electrons in the floating gate 48 to tunnel to the control gate 46. Comparing the tunneling process occurring in the FLOTOX memory cell, the tunneling of electrons here is a faster process requiring lower voltages potential across the respective terminals. Additionally, the typical erase time for the flash memory cell is less than 1 ms with approximately 14 volts applied. The erase time and/or (lower) voltage potential can be further improved by modifying and optimizing the dimensions of the memory cell.
To program the memory cell, the control gate 46 is set to be barely-on (around 2 volts), the terminal connected to region 40, away from the floating gate 46, is connected to ground, and the terminal connected to regions 42 closer to the floating gate 46 is provided with a high voltage, generally around 12 volts. In this manner, an electric field is generated in the direction of region 40 away from the floating gate, causing electrons to travel through the channel region and be injected into the floating gate 48, thereby charging the gate and programming the memory cell. The flow of the electrons in this process called hot carrier injection is as illustrated by the arrows. The programming operation by hot electron injection provides a much faster programming time when compared with the programming time of traditional FLOTOX programming operations. The typical programming time for a flash memory cell is in the range of lus (micro-second) to 100 us depending on the process, the device size, and the voltage potential applied, while the typical programming time for the FLOTOX memory cell is around 3 ms. The flash memory cell is a much faster device where time for writing data into the memory cell (Twrite) equals the time to erase the data in the memory cell (Terase) which is about 1 ms plus time to program the memory cell (Tprog) which is about 100 us. This time is faster than the write time for the FLOTOX memory cell. Moreover, a major advantage of the flash memory is that from a processing point of view, the flash memory cell requires fewer and less difficult processing steps since the self-alignment method can be used. The schematic representation of the FIG. 2a is illustrated in FIG. 2b which is the circuit symbol for the flash memory cell.
However, when flash memory cells are placed in a memory array, they have to be operated in a certain manner. Referring to FIG. 3a, a memory array 60 having a plurality of interconnected flash memory cells arranged in rows and columns is illustrated. Here, the flash memory cells are connected in such a manner that the terminals closer to the floating gates are designated as the source terminals and are connected to a single junction. The control gates of the memory cells along the same row are connected to the same word line, e.g. WL0, WL1, etc. The word lines are controlled and operated by a row address decoder 62 in response to a given row address. In a similar manner, the drain terminals of the memory cells along the same columns are connected to the same bit line, e.g. BL0, BL1, etc. The bit lines are controlled and operated by a column decoder 64 in response to a given column address (Y-MUX is a column address line multiplexer). In a read operation, the signals are amplified by a sense amplifier 66 and put into an output buffer 68. In a program operation, data is first stored in an input buffer 70 before it is passed through the column decoder 64 for storage. In order to properly program data into the memory cells, data stored in the memory cells on the same row will have to be erased before the program operation. The reason here is that the control gate of the memory cells on the same row are connected to the same word-line hence will be affected as a group. In comparison, in such a memory array using flash memory cells, the memory cells have to be altered on a large block basis (here the entire row) while a memory array using FLOTOX memory cells can be altered on a byte to byte basis. When a memory array is altered on a block basis, invariably, some of the data that does not need to be altered has to be rewritten back into the memory array which consumes time and power in the process.
The following definitions and notations are used in this disclosure to explain the operating characteristics of the various memory cells and arrays described herein:
Vsxe2x80x94Source Voltage during a read or erase operation where the low potential voltage is approximately 0 volt;
Vexe2x80x94Control Gate (CG) Erase Voltage required for F-N tunneling which is generally approximately 15 volts, depending on the process used;
Vpxe2x80x94Program Voltage applied to the drain (or source near FG side) of the memory cells; typical value is +12V depending on the process used;
Vcgpxe2x80x94CG Program Voltage, higher than the erased-cell Vte (xcx9c1.5V typical) to turn on the selected cells; Vcgp is about +2V;
Vtexe2x80x94Threshold Voltage for a cell that has been erased;
Vdp0xe2x80x94Drain Program Voltage to program the selected cells with a logical data value of xe2x80x9c0xe2x80x9dxe2x80x94meaning storing electrons into the FG Vdp0 can be either Vp (12V) or Vs (+0V) depending on the array and cell configurations;
Vdp1xe2x80x94Drain Program Voltage to program the selected cells with a logical data value of xe2x80x9c1xe2x80x9d which is the same as xe2x80x9cprogram-inhibitxe2x80x9d or do not store electrons into the FG) Vdp1 can be either Vs (0V) or Vcc (5V) depending on the array and cell configuration;
Vcgrxe2x80x94CG Read Bias Voltage with typical value of about +4V depending on the process and design;
Vdrxe2x80x94Drain Read Bias Voltage with typical value of about +1.5V to +2V;
Vccxe2x80x94Power Supply Voltage typically of +5V, depending on product and design;
Vwlexe2x80x94Erase Word Line (WL) Voltage which is  greater than =Ve+Vt (of Byte select transistor) typically and approximately +17V (assume Vt of +2V); Note that Vwle and Ve can be the same (Vwle=Ve=+17V) such that the actual voltage on the CG of the memory cells is (=Vwlexe2x88x92Vt) which is adequate for F-N tunneling;
Vwlpxe2x80x94Program WL Voltage for some of the disclosed EEPROM array (which require Vp=12V on the selected BL""s); this Vwlp greater than =Vp+Vt or about 15V typically;
Vtxe2x80x94Transistor Threshold Voltage.
To operate the memory array of FIG. 3a where flash memory cells (illustrated in FIG. 2a) are used and are configured such that the terminal near the floating gate is designated as the source terminal, Table 1a lists the voltage levels for the respective operations:
In a likewise manner, to operate the memory array of FIG. 3b where flash memory cells (illustrated in FIG. 2a) are used and are configured such that the terminal near the floating gate is designated as the drain terminal, Table 1b lists the voltage levels for the respective operations:
The flash memory cell structure requiring fewer and less difficult processing steps in the manufacturing process and providing faster erase and program time is the preferred non-volatile memory cell. However, when placed in an array, flash memory cells have to be altered on a large block basis even when part of the data does not need to be altered. Consequently, even unaltered data is required to be rewritten back to the memory cellsxe2x80x94consuming power and time in the process.
It is therefore desirable to have a memory cell with all the advantages of a flash memory cell that can be altered on a block-by-block basis, where the block size is predefined.
It is an object of the present invention to provide a memory cell with fast operational time.
It is another object of the present invention to provide a memory cell that can be fabricated with minimal number of processing steps.
It is yet another object of the present invention to provide a memory cell and array where the memory cells in the memory array can be altered on a block-by-block basis where block size is predefined.
Briefly, a presently preferred embodiment of a memory cell in accordance with the present invention comprises three regions of a first-type deposited on a substrate of a second-type, a first insulating layer deposited over the substrate and the regions, a floating gate and a control gate separated by a second insulating layer disposed over two of said regions, and a select gate disposed over two other regions. When placed in a memory array, a predefined number of memory cells can be grouped into blocks. By using a byte-select transistor, the memory cells can be accessed and altered on block by block basis. The novel memory cell structures of the present invention do not require additional processing steps aside from those required in the manufacturing of the comparable flash memory cells, and their erase and program operation times are comparable to that of comparable flash memory cells.
An advantage of the present invention is that it provides a memory cell with fast operational time.
Another advantage of the present invention is that it provides a memory cell that can be fabricated with minimal number of processing steps.
Yet another advantage of the present invention is that it provides memory cell structures and arrays where the memory cells in the memory array can be altered on a block-by-block basis where the block size is predefined.
These and other features and advantages of the present invention will become well understood upon examining the figures and reading the following detailed description of the invention.
FIG. 1a illustrates a cross-sectional side view of a conventional FLOTOX type memory cell;
FIG. 1b illustrates the schematic symbol for the conventional FLOTOX type memory cell;
FIG. 2a illustrates a cross-sectional side view of a traditional flash memory cell;
FIG. 2b illustrates the schematic symbol for the flash memory cell of FIG. 2a; 
FIG. 3a illustrates a schematic diagram of a memory array comprised of traditional flash memory cells where the terminal near the floating gate is connected as the source terminal;
FIG. 3b illustrates a schematic diagram of a memory array comprising of traditional flash memory cells where the terminal near the floating gate is connected as the drain terminal;
FIG. 4a shows a cross-sectional side view of a preferred embodiment of the memory cell of the present invention where a select transistor is connected to the non-floating side of a storage transistor;
FIG. 4b illustrates the schematic symbol for the memory cell of FIG. 4a; 
FIG. 4c illustrates a cross-sectional side view of an alternate embodiment of the memory cell of the present invention where a select transistor is connected to the floating side of a storage transistor;
FIG. 4d illustrates yet another cross-sectional side view of the alternate embodiment of FIG. 4c where the region near the floating gate is tailor shaped to minimize select transistor cell size;
FIG. 4e shows the schematic symbol for the memory cells of FIGS. 4c and 4d; 
FIG. 5a illustrates a schematic diagram of a memory array of the present invention using a memory cell of the present invention where the select transistor of the memory cell is located away from the floating gate of the storage transistor of the memory cell and is connected as a drain terminal at one junction;
FIG. 5b illustrates a schematic diagram of a memory array of the present invention using a memory cell of the present invention where the select transistor of the memory cell is located away from the floating gate of the storage transistor of the memory cell and is connected as a source terminal at one junction;
FIG. 5c illustrates a schematic diagram of a memory array of the present invention using a memory cell of the present invention where the select transistor of the memory cell is located near the floating gate of the storage transistor of the memory cell and is connected as a drain terminal at one junction;
FIG. 5d illustrates a schematic diagram of a memory array of the present invention using a memory cell of the present invention where the select transistor of the memory cell is located near the floating gate of the storage transistor of the memory cell and is connected as a source terminal at one junction;
FIG. 6 illustrates a layered cross-section view of a memory cell showing the processing steps in the manufacturing of the same; and
FIG. 7 illustrates a top view of a memory cell in accordance with the present invention.